At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
在Synopsys，我们处在改变我们工作和娱乐方式的创新的核心。自动驾驶汽车、人工智能、云5G、物联网。这些突破正引领着智能一切时代的到来。我们正用世界上最先进的芯片设计和软件安全技术为其提供动力。如果你和我们一样对创新充满热情，我们希望与你见面。
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
我们的芯片IP业务就是要更快地将更多的功能集成到soc中。我们提供世界上最广泛的芯片ip预先设计的逻辑块，内存，接口，模拟，安全和嵌入式处理器组合。这一切都是为了帮助客户集成更多的功能。满足其目标应用程序的独特性能、功率和大小要求。将差异化产品快速推向市场，降低风险。
Seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. The candidate would be working as part of a highly experienced mixed-signal design and verification team, targeting the current and next generation high speed SERDES, such as USB4.0, PCIe4.0, Ethernet, DP2.0, HDMI2.1, and MIPI MPHY products (up to 24 Gbps).
寻找一名具有高度积极性和创新精神的数字设计工程师，了解ASIC开发流程。该候选人将作为一个经验丰富的混合信号设计和验证团队的一部分工作，针对当前和下一代高速SERDES，如USB4.0, PCIe4.0，以太网，DP2.0, HDMI2.1，和MIPI MPHY产品(高达24gbps)。
在高速SERDES和数据恢复电路方面有扎实的理论和实践背景者优先。该职位提供与专业的数字和混合信号工程师团队一起工作的机会，负责提供高端混合信号设计，从规格开发到执行原型测试芯片的功能和性能测试。
ASIC Design Engineer-数字设计工程师
Key Qualifications
- Master degree in microelectronics, electronic engineering, communication or related fields;
微电子、电子工程、通信或相关专业研究生;
- Good theoretical and practical understanding of digital signal processing and data recovery circuits is required
深入理解ASIC/IP设计流程
- Familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is a plus
熟悉Verilog和VCS。熟悉后端合成工具DC/PT
- Good RTL debug capability;
良好的RTL调试能力
- Work with verification team to debug and fix RTL issues;
与验证团队一起调试和修复RTL问题;
- Scripting experience in Shell, Perl, Python and TCL is a plus
有Shell, Perl, Python和TCL脚本经验者优先
- The related products are Interface controller, High Speed DDR PHY, Static memory，Processor etc.
从事的相关产品是接口控制器 (Interface controller) / 高速DDR PHY /静态存储器/处理器 (Processor) 等
- In addition, this is a great opportunity to work with a wide suite of in-house digital design and verification tools, including VCS, Design Compiler, PrimeTime, Tetramax and so on
此外，这也是一个与 VCS, Design Compiler, PrimeTime, Tetramax 等一系列内部数字设计和验证工具合作的好机会
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.